Calculate vector address
This instruction optionally sign-extends or zero-extends the least significant 32 bits of each element from a vector of offsets or indices in the second source vector, and scales each index by 2, 4, or 8. The scaled indices are then added to a vector of base addresses from the first source vector, and the resulting addresses are placed in the destination vector. This instruction is unpredicated.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
It has encodings from 3 classes: Packed offsets , Unpacked 32-bit signed offsets and Unpacked 32-bit unsigned offsets
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| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | sz | 1 | Zm | 1 | 0 | 1 | 0 | msz | Zn | Zd | |||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32 << UInt(sz); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let d : integer = UInt(Zd); let osize : integer{} = esize; let unsigned : boolean = TRUE; let mbytes : integer{} = 1 << UInt(msz);
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| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | Zm | 1 | 0 | 1 | 0 | msz | Zn | Zd | |||||||||||||
| opc | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let d : integer = UInt(Zd); let osize : integer{} = 32; let unsigned : boolean = FALSE; let mbytes : integer{} = 1 << UInt(msz);
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| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | Zm | 1 | 0 | 1 | 0 | msz | Zn | Zd | |||||||||||||
| opc | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let d : integer = UInt(Zd); let osize : integer{} = 32; let unsigned : boolean = TRUE; let mbytes : integer{} = 1 << UInt(msz);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the base scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the offset scalable vector register, encoded in the "Zm" field. |
| <mod> |
Is the index extend and shift specifier,
encoded in
|
| <amount> |
Is the index shift amount,
encoded in
|
CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let base : bits(VL) = Z{}(n); let offs : bits(VL) = Z{}(m); var result : bits(VL); for e = 0 to elements-1 do let addr : bits(esize) = base[e*:esize]; let offselt : bits(osize) = offs[e*:esize][osize-1:0]; let offset : integer = if unsigned then UInt(offselt) else SInt(offselt); result[e*:esize] = addr + (offset * mbytes); end; Z{VL}(d) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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