AESMC

AES mix columns

This instruction reads a 16-byte state array from each 128-bit segment of the source register, and performs a single round of the MixColumns() transformation on each state array in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated.

ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented.

This instruction is legal when executed in Streaming SVE mode if one of the following is true:

SVE2
(FEAT_SVE_AES)

313029282726252423222120191817161514131211109876543210
010001010010000011100000000Zdn
sizeop

Encoding

AESMC <Zdn>.B, <Zdn>.B

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE_AES) then EndOfDecode(Decode_UNDEF); end; let dn : integer = UInt(Zdn);

Assembler Symbols

<Zdn>

Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

Operation

if IsFeatureImplemented(FEAT_SSVE_AES) then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); end; let VL : integer{} = CurrentVL(); let segments : integer = VL DIV 128; let operand : bits(VL) = Z{}(dn); var result : bits(VL); for s = 0 to segments-1 do result[s*:128] = AESMixColumns(operand[s*:128]); end; Z{VL}(dn) = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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