AND (shifted register) -- A64

This instruction performs a bitwise AND between a register value and an optionally-shifted register value, and writes the result to the destination register.

Decode for all variants of this encoding

if sf == '0' && imm6[5] == '1' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let datasize : integer{} = 32 << UInt(sf); let shift_type : ShiftType = DecodeShift(shift); let shift_amount : integer = UInt(imm6);

Assembler Symbols

<Wd>	Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn>	Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.

<Wm>	Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.

<shift>

Is the optional shift to be applied to the final source, defaulting to LSL and encoded in shift:

shift	<shift>
00	LSL
01	LSR
10	ASR
11	ROR

<amount>	For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
	For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.

<Xd>	Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn>	Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.

<Xm>	Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.

Operation

let operand1 : bits(datasize) = X{}(n); let operand2 : bits(datasize) = ShiftReg{}(m, shift_type, shift_amount); X{datasize}(d) = operand1 AND operand2;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

2026-03_rel 2026-03-26 20:48:11

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
sf	0	0	0	1	0	1	0	shift		0	Rm					imm6						Rn					Rd
	opc									N