Bit clear and exclusive-OR
This instruction performs a bitwise AND between the 128-bit vector in a source SIMD&FP register and the complement of the vector in another source SIMD&FP register, then performs a bitwise exclusive-OR between the resulting vector and the vector in a third source SIMD&FP register, and writes the result to the destination SIMD&FP register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | Rm | 0 | Ra | Rn | Rd | ||||||||||||||||
| Op0 | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SHA3) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let a : integer{} = UInt(Ra);
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Vm> |
Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
| <Va> |
Is the name of the third SIMD&FP source register, encoded in the "Ra" field. |
AArch64_CheckFPAdvSIMDEnabled(); let operand1 : bits(128) = V{}(m); let operand2 : bits(128) = V{}(n); let operand3 : bits(128) = V{}(a); V{128}(d) = operand2 XOR (operand1 AND NOT(operand3));
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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