Single-precision convert to BFloat16 (scalar)
This instruction converts the single-precision floating-point value in the 32-bit SIMD&FP source register to BFloat16 format and writes the result in the 16-bit SIMD&FP destination register.
ID_AA64ISAR1_EL1.BF16 indicates whether this instruction is supported.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | Rn | Rd | ||||||||
| M | S | ftype | opcode | ||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_BF16) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn);
| <Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Sn> |
Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
AArch64_CheckFPEnabled(); let operand : bits(32) = V{}(n); let merge : boolean = IsMerging(FPCR()); var result : bits(128) = if merge then V{128}(d) else Zeros{128}; result[0+:16] = FPConvertBF(operand, FPCR()); V{128}(d) = result;
2026-03_rel 2026-03-26 20:48:11
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