Single-precision convert to BFloat16 (vector)
This instruction reads each single-precision element in the SIMD&FP source vector, converts each value to BFloat16 format, and writes the results in the lower or upper half of the SIMD&FP destination vector. The result elements are half the width of the source elements.
The BFCVTN instruction writes the half-width results to the lower half of the 128-bit SIMD&FP destination vector and clears the upper half to zero. The BFCVTN2 instruction writes the results to the upper half of the 128-bit SIMD&FP destination vector without affecting the lower half.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | Rn | Rd | ||||||||
| U | size | opcode | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_BF16) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let part : integer = UInt(Q); let elements : integer = 64 DIV 16;
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Ta> |
Is an arrangement specifier,
encoded in
|
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
AArch64_CheckFPAdvSIMDEnabled(); let operand : bits(128) = V{}(n); var result : bits(64); for e = 0 to elements-1 do result[e*:16] = FPConvertBF(operand[e*:32], FPCR()); end; Vpart{64}(d, part) = result;
2026-03_rel 2026-03-26 20:48:11
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