BFDOT (vectors)

BFloat16 dot product to single-precision

This instruction delimits the source vectors into pairs of BFloat16 elements.

If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction:

If FEAT_EBF16 is implemented and FPCR.EBF is 1, this instruction:

Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction:

This instruction is unpredicated.

ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.

SVE
((FEAT_SVE || FEAT_SME) && FEAT_BF16)

313029282726252423222120191817161514131211109876543210
01100100011Zm100000ZnZda
opo2

Encoding

BFDOT <Zda>.S, <Zn>.H, <Zm>.H

Decode for this encoding

if ((!IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME)) || !IsFeatureImplemented(FEAT_BF16)) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda);

Assembler Symbols

<Zda>

Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV 32; let operand1 : bits(VL) = Z{}(n); let operand2 : bits(VL) = Z{}(m); let operand3 : bits(VL) = Z{}(da); var result : bits(VL); for e = 0 to elements-1 do let elt1_a : bits(16) = operand1[(2 * e + 0)*:16]; let elt1_b : bits(16) = operand1[(2 * e + 1)*:16]; let elt2_a : bits(16) = operand2[(2 * e + 0)*:16]; let elt2_b : bits(16) = operand2[(2 * e + 1)*:16]; var sum : bits(32) = operand3[e*:32]; sum = BFDotAdd(sum, elt1_a, elt1_b, elt2_a, elt2_b, FPCR()); result[e*:32] = sum; end; Z{VL}(da) = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:


2026-03_rel 2026-03-26 20:48:11

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