BFloat16 fused multiply-add by indexed element
This instruction multiplies all BFloat16 elements within each 128-bit segment of the first source vector by the specified element in the corresponding second source vector segment. The products are then destructively added without intermediate rounding to the corresponding elements of the addend and destination vector.
The elements within the second source vector are specified using an immediate index that selects the same element position within each 128-bit vector segment. The index range is from 0 to 7.
This instruction follows SVE2 non-widening BFloat16 numerical behaviors.
This instruction is unpredicated.
ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | i3h | 1 | i3l | Zm | 0 | 0 | 0 | 0 | 1 | 0 | Zn | Zda | |||||||||||
| o2 | op | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE_B16B16) then EndOfDecode(Decode_UNDEF); end; let index : integer = UInt(i3h::i3l); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda); let op1_neg : boolean = FALSE; let op3_neg : boolean = FALSE;
| <Zda> |
Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. |
| <imm> |
Is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields. |
if IsFeatureImplemented(FEAT_SME2) then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); end; let VL : integer{} = CurrentVL(); let elements : integer = VL DIV 16; let eltspersegment : integer = 128 DIV 16; let op1 : bits(VL) = Z{}(n); let op2 : bits(VL) = Z{}(m); var result : bits(VL) = Z{}(da); for e = 0 to elements-1 do let segmentbase : integer = e - (e MOD eltspersegment); let s : integer = segmentbase + index; let elem2 : bits(16) = op2[s*:16]; let elem1 : bits(16) = if op1_neg then BFNeg(op1[e*:16]) else op1[e*:16]; let elem3 : bits(16) = if op3_neg then BFNeg(result[e*:16]) else result[e*:16]; result[e*:16] = BFMulAdd(elem3, elem1, elem2, FPCR()); end; Z{VL}(da) = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:
2026-03_rel 2026-03-26 20:48:11
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