BFMLALB, BFMLALT (by element) -- A64

This instruction widens the even-numbered (bottom) or odd-numbered (top) 16-bit elements in the first source vector, and the indexed element in the second source vector from Bfloat16 to single-precision format. The instruction then multiplies and adds these values without intermediate rounding to single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the first source vector.

Vector
(FEAT_BF16)

Decode for this encoding

if !IsFeatureImplemented(FEAT_BF16) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Rn); let m : integer = UInt('0'::Rm); let d : integer = UInt(Rd); let index : integer = UInt(H::L::M); let elements : integer = 128 DIV 32; let sel : integer = UInt(Q);

Assembler Symbols

<bt>

Is the bottom or top element specifier, encoded in Q:

Q	<bt>
0	B
1	T

<Vd>	Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn>	Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>	Is the name of the second SIMD&FP source register, in the range V0 to V15, encoded in the "Rm" field.

<index>

Is the element index, in the range 0 to 7, encoded in the "H:L:M" fields.

Operation

AArch64_CheckFPAdvSIMDEnabled(); var result : bits(128); let operand1 : bits(128) = V{}(n); let operand2 : bits(128) = V{}(m); let operand3 : bits(128) = V{}(d); let element2 : bits(16) = operand2[index*:16]; for e = 0 to elements-1 do let element1 : bits(16) = operand1[(2 * e + sel)*:16]; let addend : bits(32) = operand3[e*:32]; result[e*:32] = BFMulAddH(addend, element1, element2, FPCR()); end; V{128}(d) = result;

2026-03_rel 2026-03-26 20:48:11

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	Q	0	0	1	1	1	1	1	1	L	M	Rm				1	1	1	1	H	0	Rn					Rd
		U						size								opcode