BFSUB

Multi-vector BFloat16 subtract from ZA array vectors

This instruction destructively subtracts all elements of the two or four source vectors from the corresponding BFloat16 elements of the ZA single-vector groups.

The single-vector group within each half of or each quarter of the ZA array is selected by the sum of the vector select register and offset, modulo half or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

This instruction follows SME2 ZA-targeting non-widening BFloat16 numerical behaviors.

This instruction is unpredicated.

ID_AA64SMFR0_EL1.B16B16 indicates whether this instruction is implemented.

It has encodings from 2 classes: Two ZA single-vectors and Four ZA single-vectors

Two ZA single-vectors
(FEAT_SME_B16B16)

313029282726252423222120191817161514131211109876543210
11000001111001000Rv111Zm001off3
szS

Encoding

BFSUB ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_B16B16) then EndOfDecode(Decode_UNDEF); end; let v : integer = UInt('010'::Rv); let m : integer = UInt(Zm::'0'); let offset : integer = UInt(off3); let nreg : integer{} = 2;

Four ZA single-vectors
(FEAT_SME_B16B16)

313029282726252423222120191817161514131211109876543210
11000001111001010Rv111Zm0001off3
szS

Encoding

BFSUB ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_B16B16) then EndOfDecode(Decode_UNDEF); end; let v : integer = UInt('010'::Rv); let m : integer = UInt(Zm::'00'); let offset : integer = UInt(off3); let nreg : integer{} = 4;

Assembler Symbols

<Wv>

Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.

<offs>

Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.

<Zm1>

For the "Two ZA single-vectors" variant: is the name of the first scalable vector register of the source multi-vector group, encoded as "Zm" times 2.

For the "Four ZA single-vectors" variant: is the name of the first scalable vector register of the source multi-vector group, encoded as "Zm" times 4.

<Zm2>

Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zm" times 2 plus 1.

<Zm4>

Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zm" times 4 plus 3.

Operation

CheckStreamingSVEAndZAEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV 16; let vectors : integer = VL DIV 8; let vstride : integer = vectors DIV nreg; let vbase : bits(32) = X{}(v); var vec : integer = (UInt(vbase) + offset) MOD vstride; var result : bits(VL); for r = 0 to nreg-1 do let operand1 : bits(VL) = ZAvector{}(vec); let operand2 : bits(VL) = Z{}(m+r); for e = 0 to elements-1 do let element1 : bits(16) = operand1[e*:16]; let element2 : bits(16) = operand2[e*:16]; result[e*:16] = BFSub_ZA(element1, element2, FPCR()); end; ZAvector{VL}(vec) = result; vec = vec + vstride; end;


2026-03_rel 2026-03-26 20:48:11

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