BRKBS

Break before first true condition, setting the condition flags

This instruction sets the destination predicate elements up to but not including the first active and true source element to true, then sets subsequent elements to false. Inactive elements in the destination predicate register are set to zero. This instruction sets the First (N), None (Z), and !Last (C) condition flags based on the predicate result, and sets the V flag to zero.

Setting the condition flags
(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
001001011101000001Pg0Pn0Pd
BSM

Encoding

BRKBS <Pd>.B, <Pg>/Z, <Pn>.B

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8; let g : integer = UInt(Pg); let n : integer = UInt(Pn); let d : integer = UInt(Pd); let merging : boolean = FALSE; let setflags : boolean = TRUE;

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<Pg>

Is the name of the governing scalable predicate register, encoded in the "Pg" field.

<Pn>

Is the name of the source scalable predicate register, encoded in the "Pn" field.

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); let operand : bits(PL) = P{}(n); let operand2 : bits(PL) = if merging then P{PL}(d) else Zeros{PL}; var break : boolean = FALSE; var result : bits(PL); let psize : integer{} = esize DIV 8; for e = 0 to elements-1 do let element : boolean = ActivePredicateElement{PL}(operand, e, esize); if ActivePredicateElement{PL}(mask, e, esize) then break = break || element; let pbit : bit = if !break then '1' else '0'; result[e*:psize] = ZeroExtend{psize}(pbit); elsif merging then let pbit : bit = PredicateElement{PL}(operand2, e, esize); result[e*:psize] = ZeroExtend{psize}(pbit); else result[e*:psize] = ZeroExtend{psize}('0'); end; end; if setflags then PSTATE.[N,Z,C,V] = PredTest{PL}(mask, result, esize); end; P{PL}(d) = result;

Operational information

If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the NZCV condition flags written by this instruction might be significantly delayed.


2026-03_rel 2026-03-26 20:48:11

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