CLASTA (SIMD&FP scalar) -- A64

This instruction extracts and zero-extends the element after the Last active element, or if the Last active element is the final element it extracts element zero, from the source vector register, and destructively places the zero-extended value in the destination and first source SIMD & floating-point scalar register. If there are no Active elements, the least significant element-size bits of the destination and first source SIMD & floating-point scalar register are destructively zero-extended.

SVE
(FEAT_SVE || FEAT_SME)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let dn : integer = UInt(Vdn); let m : integer = UInt(Zm); let isBefore : boolean = FALSE;

Assembler Symbols

<V>

Is a width specifier, encoded in size:

size	<V>
00	B
01	H
10	S
11	D

<dn>	Is the number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field.

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zm>	Is the name of the source scalable vector register, encoded in the "Zm" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	D

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); let operand1 : bits(esize) = V{}(dn); let operand2 : bits(VL) = Z{}(m); var result : bits(esize); var last : integer = LastActiveElement{PL}(mask, esize); if last < 0 then result = ZeroExtend{esize}(operand1); else if !isBefore then last = last + 1; if last >= elements then last = 0; end; end; result = operand2[last*:esize]; end; V{esize}(dn) = result;

2026-03_rel 2026-03-26 20:48:11

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	1	size		1	0	1	0	1	0	1	0	0	Pg			Zm					Vdn
															B