CMP<cc> (wide elements) -- A64

This instruction compares active integer elements in the first source vector with overlapping 64-bit doubleword elements in the second source vector, and places the boolean results of the specified comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. This instruction sets the First (N), None (Z), and !Last (C) condition flags based on the predicate result, and sets the V flag to zero.

<cc>	Comparison
EQ	equal
GE	signed greater than or equal
GT	signed greater than
HI	unsigned higher than
HS	unsigned higher than or same
LE	signed less than or equal
LO	unsigned lower than
LS	unsigned lower than or same
LT	signed less than
NE	not equal

Equal
(FEAT_SVE || FEAT_SME)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; if size == '11' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let d : integer = UInt(Pd); let cmp_op : CmpOp = Cmp_EQ; let unsigned : boolean = FALSE;

Greater than
(FEAT_SVE || FEAT_SME)

Decode for this encoding

Greater than or equal
(FEAT_SVE || FEAT_SME)

Decode for this encoding

Higher
(FEAT_SVE || FEAT_SME)

Decode for this encoding

Higher or same
(FEAT_SVE || FEAT_SME)

Decode for this encoding

Less than
(FEAT_SVE || FEAT_SME)

Decode for this encoding

Less than or equal
(FEAT_SVE || FEAT_SME)

Decode for this encoding

Lower
(FEAT_SVE || FEAT_SME)

Decode for this encoding

Lower or same
(FEAT_SVE || FEAT_SME)

Decode for this encoding

Not equal
(FEAT_SVE || FEAT_SME)

Decode for this encoding

Assembler Symbols

<Pd>	Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	RESERVED

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>	Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>	Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); let operand1 : bits(VL) = if AnyActiveElement{PL}(mask, esize) then Z{VL}(n) else Zeros{VL}; let operand2 : bits(VL) = if AnyActiveElement{PL}(mask, esize) then Z{VL}(m) else Zeros{VL}; var result : bits(PL); let psize : integer{} = esize DIV 8; for e = 0 to elements-1 do let op1elt : bits(esize) = operand1[e*:esize]; let element1 : integer = if unsigned then UInt(op1elt) else SInt(op1elt); if ActivePredicateElement{PL}(mask, e, esize) then var cond : boolean; let op2elt : bits(64) = operand2[((e * esize) DIVRM 64)*:64]; let element2 : integer = if unsigned then UInt(op2elt) else SInt(op2elt); case cmp_op of when Cmp_EQ => cond = element1 == element2; when Cmp_NE => cond = element1 != element2; when Cmp_GE => cond = element1 >= element2; when Cmp_LT => cond = element1 < element2; when Cmp_GT => cond = element1 > element2; when Cmp_LE => cond = element1 <= element2; end; let pbit : bit = if cond then '1' else '0'; result[e*:psize] = ZeroExtend{psize}(pbit); else result[e*:psize] = ZeroExtend{psize}('0'); end; end; PSTATE.[N,Z,C,V] = PredTest{PL}(mask, result, esize); P{PL}(d) = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the predicate register or NZCV condition flags written by this instruction might be significantly delayed.

2026-03_rel 2026-03-26 20:48:11

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	0	0	1	0	0	size		0	Zm					0	0	1	Pg			Zn					0	Pd
																op		o2									ne

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	0	0	1	0	0	size		0	Zm					0	1	0	Pg			Zn					1	Pd
																U		lt									ne

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	0	0	1	0	0	size		0	Zm					0	1	0	Pg			Zn					0	Pd
																U		lt									ne

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	0	0	1	0	0	size		0	Zm					1	1	0	Pg			Zn					1	Pd
																U		lt									ne

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	0	0	1	0	0	size		0	Zm					1	1	0	Pg			Zn					0	Pd
																U		lt									ne