CSET

Conditional set

This instruction sets the destination register to 1 if the condition is TRUE, and otherwise sets it to 0.

This is an alias of CSINC. This means:

313029282726252423222120191817161514131211109876543210
sf001101010011111!= 111x0111111Rd
opSRmcondo2Rn

Encoding for the 32-bit variant

Applies when (sf == 0)

CSET <Wd>, <invcond>

is equivalent to

CSINC <Wd>, WZR, WZR, <cond>

and is always the preferred disassembly.

Encoding for the 64-bit variant

Applies when (sf == 1)

CSET <Xd>, <invcond>

is equivalent to

CSINC <Xd>, XZR, XZR, <cond>

and is always the preferred disassembly.

Assembler Symbols

<Wd>

Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<invcond>

Is one of the standard conditions, excluding AL and NV, encoded with its least significant bit inverted, and encoded in cond:

cond <invcond> Description
0000 NE

Maps to <cond> EQ.

0001 EQ

Maps to <cond> NE.

0010 CC

Maps to <cond> CS.

0011 CS

Maps to <cond> CC.

0100 PL

Maps to <cond> MI.

0101 MI

Maps to <cond> PL.

0110 VC

Maps to <cond> VS.

0111 VS

Maps to <cond> VC.

1000 LS

Maps to <cond> HI.

1001 HI

Maps to <cond> LS.

1010 LT

Maps to <cond> GE.

1011 GE

Maps to <cond> LT.

1100 LE

Maps to <cond> GT.

1101 GT

Maps to <cond> LE.

<Xd>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

Operation

The description of CSINC gives the operational pseudocode for this instruction.

Operational Information

The description of CSINC gives the operational information for this instruction.


2026-03_rel 2026-03-26 20:48:11

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