Data memory barrier
This instruction is a memory barrier that ensures the ordering of observations of memory accesses, see Data Memory Barrier.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | CRm | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | |||
| opc | Rt | ||||||||||||||||||||||||||||||
var types : MBReqTypes; case CRm[1:0] of when '00' => types = MBReqTypes_All; when '01' => types = MBReqTypes_Reads; when '10' => types = MBReqTypes_Writes; when '11' => types = MBReqTypes_All; end;
| <option> |
Specifies the limitation on the Memory Effects ordered by the barrier operation, and is encoded in "CRm". For more information on whether a Memory Effect is before or after a barrier instruction, see Data Memory Barrier (DMB).
|
| <imm> |
Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "CRm" field. |
2026-03_rel 2026-03-26 20:48:11
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