DUP (element)

Duplicate vector element to vector or scalar

This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

This instruction is used by the alias MOV (scalar).

It has encodings from 2 classes: Scalar and Vector

Scalar
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
01011110000imm5000001RnRd
opimm4

Encoding

DUP <V><d>, <Vn>.<T>[<index>]

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if imm5 == 'x0000' then EndOfDecode(Decode_UNDEF); end; let size : integer{} = LowestSetBitNZ(imm5[3:0]); let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let index : integer = UInt(imm5[4:size+1]); let idxdsize : integer{} = 64 << UInt(imm5[4]); let esize : integer{} = 8 << size; let datasize : integer{} = esize; let elements : integer = 1;

Vector
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
0Q001110000imm5000001RnRd
opimm4

Encoding

DUP <Vd>.<T>, <Vn>.<Ts>[<index>]

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if imm5 == 'x0000' then EndOfDecode(Decode_UNDEF); end; if imm5 == 'x1000' && Q == '0' then EndOfDecode(Decode_UNDEF); end; let size : integer{} = LowestSetBitNZ(imm5[3:0]); let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let index : integer = UInt(imm5[4:size+1]); let idxdsize : integer{} = 64 << UInt(imm5[4]); let esize : integer{} = 8 << size; let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV esize;

Assembler Symbols

<V>

Is the destination width specifier, encoded in imm5:

imm5 <V>
x0000 RESERVED
xxxx1 B
xxx10 H
xx100 S
x1000 D
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<T>

For the "Scalar" variant: is the element width specifier, encoded in imm5:

imm5 <T>
x0000 RESERVED
xxxx1 B
xxx10 H
xx100 S
x1000 D

For the "Vector" variant: is an arrangement specifier, encoded in (imm5 :: Q):

imm5 Q <T>
x0000 x RESERVED
xxxx1 0 8B
xxxx1 1 16B
xxx10 0 4H
xxx10 1 8H
xx100 0 2S
xx100 1 4S
x1000 0 RESERVED
x1000 1 2D
<index>

Is the element index encoded in imm5:

imm5 <index>
x0000 RESERVED
xxxx1 UInt(imm5[4:1])
xxx10 UInt(imm5[4:2])
xx100 UInt(imm5[4:3])
x1000 UInt(imm5[4])
<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ts>

Is an element size specifier, encoded in imm5:

imm5 <Ts>
x0000 RESERVED
xxxx1 B
xxx10 H
xx100 S
x1000 D

Operation

AArch64_CheckFPAdvSIMDEnabled(); let operand : bits(idxdsize) = V{}(n); var result : bits(datasize); var element : bits(esize); element = operand[index*:esize]; for e = 0 to elements-1 do result[e*:esize] = element; end; V{datasize}(d) = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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