Duplicate general-purpose register to vector
This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | 0 | 0 | 0 | 1 | 1 | Rn | Rd | ||||||||||||
| op | imm4 | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if imm5 == 'x0000' then EndOfDecode(Decode_UNDEF); end; if imm5 == 'x1000' && Q == '0' then EndOfDecode(Decode_UNDEF); end; let size : integer{} = LowestSetBitNZ(imm5[3:0]); let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); // imm5<4:size+1> is IGNORED let esize : integer{} = 8 << size; let datasize : integer{} = 64 << UInt(Q);
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <T> |
Is an arrangement specifier,
encoded in
|
| <n> |
Is the number [0-30] of the general-purpose source register or ZR (31), encoded in the "Rn" field. |
AArch64_CheckFPAdvSIMDEnabled(); let element : bits(esize) = X{}(n); let elements : integer = datasize DIV esize; var result : bits(datasize); for e = 0 to elements-1 do result[e*:esize] = element; end; V{datasize}(d) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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