8-bit floating-point convert to half-precision (vector)
This instruction converts each 8-bit floating-point element from the lower or upper half of the source vector to half-precision while downscaling the value, and places the results in the 16-bit elements of the destination vector. F1CVTL and F2CVTL convert the elements from the lower half of the source vector while scaling the values by 2-UInt(FPMR.LSCALE[3:0]) and 2-UInt(FPMR.LSCALE2[3:0]), respectively. F1CVTL2 and F2CVTL2 convert the elements from the upper half of the source vector while scaling the values by 2-UInt(FPMR.LSCALE[3:0]) and 2-UInt(FPMR.LSCALE2[3:0]), respectively.
The 8-bit floating-point encoding format for F1CVTL and F1CVTL2 is selected by FPMR.F8S1. The 8-bit floating-point encoding format for F2CVTL and F2CVTL2 is selected by FPMR.F8S2.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 0 | x | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | Rn | Rd | ||||||||
| U | size | opcode | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP8) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Rn); let d : integer = UInt(Rd); let part : integer = UInt(Q); let elements : integer = 64 DIV 8; let issrc2 : boolean = size == '01';
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
| <Ta> |
Is an arrangement specifier,
encoded in
|
CheckFPMREnabled(); AArch64_CheckFPAdvSIMDEnabled(); let operand : bits(64) = Vpart{}(n, part); var result : bits(128); for e = 0 to elements-1 do result[e*:16] = FP8ConvertFP(operand[e*:8], issrc2, FPCR(), FPMR()); end; V{128}(d) = result;
2026-03_rel 2026-03-26 20:48:11
Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.