FAC<cc>

Floating-point absolute compare

This instruction compares active absolute values of floating-point elements in the first source vector with the corresponding absolute values of elements in the second source vector, and places the boolean results of the specified comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. This instruction does not set the condition flags.

<cc> Comparison
GE greater than or equal
GT greater than
LE less than or equal
LT less than

This instruction is used by the pseudo-instructions FACLE, and FACLT.

It has encodings from 2 classes: Greater than and Greater than or equal

Greater than
(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
01100101size0Zm111PgZn1Pd
opo2o3

Encoding

FACGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; if size == '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let d : integer = UInt(Pd); let cmp_op : CmpOp = Cmp_GT;

Greater than or equal
(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
01100101size0Zm110PgZn1Pd
opo2o3

Encoding

FACGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; if size == '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let d : integer = UInt(Pd); let cmp_op : CmpOp = Cmp_GE;

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 RESERVED
01 H
10 S
11 D
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); let operand1 : bits(VL) = if AnyActiveElement{PL}(mask, esize) then Z{VL}(n) else Zeros{VL}; let operand2 : bits(VL) = if AnyActiveElement{PL}(mask, esize) then Z{VL}(m) else Zeros{VL}; var result : bits(PL); let psize : integer{} = esize DIV 8; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then let element1 : bits(esize) = FPAbs{}(operand1[e*:esize], FPCR()); let element2 : bits(esize) = FPAbs{}(operand2[e*:esize], FPCR()); var res : boolean; case cmp_op of when Cmp_GE => res = FPCompareGE{esize}(element1, element2, FPCR()); when Cmp_GT => res = FPCompareGT{esize}(element1, element2, FPCR()); end; let pbit : bit = if res then '1' else '0'; result[e*:psize] = ZeroExtend{psize}(pbit); else result[e*:psize] = ZeroExtend{psize}('0'); end; end; P{PL}(d) = result;

Operational information

If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the predicate register written by this instruction might be significantly delayed.


2026-03_rel 2026-03-26 20:48:11

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