Floating-point add strictly-ordered reduction, accumulating in scalar
This instruction adds the floating-point values in a SIMD&FP scalar source and all active lanes of the vector source and destructively places the result in the SIMD&FP scalar source register. Vector elements are processed strictly in order from low to high, with the scalar source providing the initial value. Inactive elements in the source vector are ignored.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | size | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | Pg | Zm | Vdn | |||||||||||
| opc | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; if size == '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let dn : integer = UInt(Vdn); let m : integer = UInt(Zm);
| <V> |
Is a width specifier,
encoded in
|
| <dn> |
Is the number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zm> |
Is the name of the source scalable vector register, encoded in the "Zm" field. |
| <T> |
Is the size specifier,
encoded in
|
CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); let operand1 : bits(esize) = V{}(dn); let operand2 : bits(VL) = if AnyActiveElement{PL}(mask, esize) then Z{VL}(m) else Zeros{VL}; var result : bits(esize) = operand1; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then let element : bits(esize) = operand2[e*:esize]; result = FPAdd{esize}(result, element, FPCR()); end; end; V{esize}(dn) = result;
2026-03_rel 2026-03-26 20:48:11
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