FCLAMP

Multi-vector floating-point clamp to minimum/maximum number

This instruction clamps each floating-point element in the two or four destination vectors to between the floating-point minimum value in the corresponding element of the first source vector and the floating-point maximum value in the corresponding element of the second source vector and destructively places the clamped results in the corresponding elements of the two or four destination vectors.

Regardless of the value of FPCR.AH, the behavior is as follows for each minimum number and maximum number operation:

This instruction follows SME2 floating-point numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors.

This instruction is unpredicated.

It has encodings from 2 classes: Two registers and Four registers

Two registers
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001!= 001Zm110000ZnZd0
sizeop

Encoding

FCLAMP { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<T>, <Zm>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let d : integer = UInt(Zd::'0'); let nreg : integer{} = 2;

Four registers
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001!= 001Zm110010ZnZd00
sizeop

Encoding

FCLAMP { <Zd1>.<T>-<Zd4>.<T> }, <Zn>.<T>, <Zm>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let d : integer = UInt(Zd::'00'); let nreg : integer{} = 4;

Assembler Symbols

<Zd1>

For the "Two registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.

For the "Four registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.

<T>

Is the size specifier, encoded in size:

size <T>
01 H
10 S
11 D
<Zd2>

Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

<Zd4>

Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.

Operation

CheckStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; var results : array [[4]] of bits(VL); for r = 0 to nreg-1 do let operand1 : bits(VL) = Z{}(n); let operand2 : bits(VL) = Z{}(m); let operand3 : bits(VL) = Z{}(d+r); for e = 0 to elements-1 do let element1 : bits(esize) = operand1[e*:esize]; let element2 : bits(esize) = operand2[e*:esize]; let element3 : bits(esize) = operand3[e*:esize]; let maxelement : bits(esize) = FPMaxNum{}(element1, element3, FPCR()); results[[r]][e*:esize] = FPMinNum{esize}(maxelement, element2, FPCR()); end; end; for r = 0 to nreg-1 do Z{VL}(d+r) = results[[r]]; end;


2026-03_rel 2026-03-26 20:48:11

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