Floating-point compare greater than or equal to zero (vector)
This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 4 classes: Scalar half-precision , Scalar single-precision and double-precision , Vector half-precision and Vector single-precision and double-precision
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| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | ||||||||
| U | a | op | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 16; let datasize : integer{} = esize; let elements : integer = 1;
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| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | sz | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | ||||||||
| U | op | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 32 << UInt(sz); let datasize : integer{} = esize; let elements : integer = 1;
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| 0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | ||||||||
| U | a | op | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 16; let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV esize;
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| 0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 1 | sz | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | ||||||||
| U | op | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if sz::Q == '10' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 32 << UInt(sz); let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV esize;
| <Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Hn> |
Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
| <V> |
Is a width specifier,
encoded in
|
| <d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
| <n> |
Is the number of the SIMD&FP source register, encoded in the "Rn" field. |
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
AArch64_CheckFPAdvSIMDEnabled(); let operand : bits(datasize) = V{}(n); var result : bits(datasize); let zero : bits(esize) = FPZero{}('0'); var element : bits(esize); var test_passed : boolean; for e = 0 to elements-1 do element = operand[e*:esize]; test_passed = FPCompareGE{esize}(element, zero, FPCR()); result[e*:esize] = if test_passed then Ones{esize} else Zeros{esize}; end; V{datasize}(d) = result;
2026-03_rel 2026-03-26 20:48:11
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