FCMLA

Floating-point complex multiply accumulate

This instruction operates on complex numbers that are represented in SIMD&FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following calculation on the corresponding complex number element pairs from the two source registers and the destination register:

The multiplication and addition operations are performed as a fused multiply-add, without any intermediate rounding.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Vector
(FEAT_FCMA)

313029282726252423222120191817161514131211109876543210
0Q101110size0Rm110rot1RnRd
U

Encoding

FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate>

Decode for this encoding

if !IsFeatureImplemented(FEAT_FCMA) then EndOfDecode(Decode_UNDEF); end; if size == '00' then EndOfDecode(Decode_UNDEF); end; if !IsFeatureImplemented(FEAT_FP16) && size == '01' then EndOfDecode(Decode_UNDEF); end; if Q == '0' && size == '11' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV esize;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in (size :: Q):

size Q <T>
00 x RESERVED
01 0 4H
01 1 8H
10 0 2S
10 1 4S
11 0 RESERVED
11 1 2D
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

<rotate>

Is the rotation, encoded in rot:

rot <rotate>
00 0
01 90
10 180
11 270

Operation

AArch64_CheckFPAdvSIMDEnabled(); let operand1 : bits(datasize) = V{}(n); let operand2 : bits(datasize) = V{}(m); let operand3 : bits(datasize) = V{}(d); var result : bits(datasize); var element1 : bits(esize); var element2 : bits(esize); var element3 : bits(esize); var element4 : bits(esize); for e = 0 to (elements DIV 2)-1 do case rot of when '00' => element1 = operand2[(e*2)*:esize]; element2 = operand1[(e*2)*:esize]; element3 = operand2[(e*2+1)*:esize]; element4 = operand1[(e*2)*:esize]; when '01' => element1 = FPNeg{esize}(operand2[(e*2+1)*:esize], FPCR()); element2 = operand1[(e*2+1)*:esize]; element3 = operand2[(e*2)*:esize]; element4 = operand1[(e*2+1)*:esize]; when '10' => element1 = FPNeg{esize}(operand2[(e*2)*:esize], FPCR()); element2 = operand1[(e*2)*:esize]; element3 = FPNeg{esize}(operand2[(e*2+1)*:esize], FPCR()); element4 = operand1[(e*2)*:esize]; when '11' => element1 = operand2[(e*2+1)*:esize]; element2 = operand1[(e*2+1)*:esize]; element3 = FPNeg{esize}(operand2[(e*2)*:esize], FPCR()); element4 = operand1[(e*2+1)*:esize]; end; result[(e*2)*:esize] = FPMulAdd{esize}(operand3[(e*2)*:esize], element2, element1, FPCR()); result[(e*2+1)*:esize] = FPMulAdd{esize}(operand3[(e*2+1)*:esize], element4, element3, FPCR()); end; V{datasize}(d) = result;


2026-03_rel 2026-03-26 20:48:11

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