FCMLA (vectors)

Floating-point complex multiply-add (predicated)

This instruction multiplies the duplicated real components for rotations 0 and 180, or imaginary components for rotations 90 and 270, of the floating-point complex numbers in the first source vector by the corresponding complex number in the second source vector rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation.

This instruction then destructively adds the products to the corresponding components of the complex numbers in the addend and destination vector, without intermediate rounding.

These transformations permit the creation of a variety of multiply-add and multiply-subtract operations on complex numbers by combining two of these instructions with the same vector operands but with rotations that are 90 degrees apart.

Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element. Inactive elements in the destination vector register remain unmodified.

SVE
(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
01100100size0Zm0rotPgZnZda

Encoding

FCMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, <const>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; if size == '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda); let sel_a : integer = UInt(rot[0]); let sel_b : integer = UInt(NOT(rot[0])); let neg_i : boolean = (rot[1] == '1'); let neg_r : boolean = (rot[0] != rot[1]);

Assembler Symbols

<Zda>

Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 RESERVED
01 H
10 S
11 D
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

<const>

Is the const specifier, encoded in rot:

rot <const>
00 #0
01 #90
10 #180
11 #270

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let pairs : integer = VL DIV (2 * esize); let mask : bits(PL) = P{}(g); let op1 : bits(VL) = if AnyActiveElement{PL}(mask, esize) then Z{VL}(n) else Zeros{VL}; let op2 : bits(VL) = if AnyActiveElement{PL}(mask, esize) then Z{VL}(m) else Zeros{VL}; let op3 : bits(VL) = Z{}(da); var result : bits(VL); for p = 0 to pairs-1 do var addend_r : bits(esize) = op3[(2 * p + 0)*:esize]; var addend_i : bits(esize) = op3[(2 * p + 1)*:esize]; if ActivePredicateElement{PL}(mask, 2 * p + 0, esize) then let elt1_a : bits(esize) = op1[(2*p + sel_a)*:esize]; let elt2_a : bits(esize) = (if neg_r then FPNeg{esize}(op2[(2 * p + sel_a)*:esize], FPCR()) else op2[(2 * p + sel_a)*:esize]); addend_r = FPMulAdd{esize}(addend_r, elt1_a, elt2_a, FPCR()); end; if ActivePredicateElement{PL}(mask, 2 * p + 1, esize) then let elt1_a : bits(esize) = op1[(2 * p + sel_a)*:esize]; let elt2_b : bits(esize) = (if neg_i then FPNeg{esize}(op2[(2 * p + sel_b)*:esize], FPCR()) else op2[(2 * p + sel_b)*:esize]); addend_i = FPMulAdd{esize}(addend_i, elt1_a, elt2_b, FPCR()); end; result[(2 * p + 0)*:esize] = addend_r; result[(2 * p + 1)*:esize] = addend_i; end; Z{VL}(da) = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:


2026-03_rel 2026-03-26 20:48:11

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