Floating-point convert precision (scalar)
This instruction converts the floating-point value in the SIMD&FP source register to the precision for the destination register data type using the rounding mode that is determined by the FPCR and writes the result to the SIMD&FP destination register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 1 | 0 | 0 | 0 | 1 | opc | 1 | 0 | 0 | 0 | 0 | Rn | Rd | ||||||||||
| M | S | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if ftype == opc || ftype == '10' || opc == '10' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let srcsize : integer{} = 8 << UInt(ftype XOR '10'); let dstsize : integer{} = 8 << UInt(opc XOR '10');
| <Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Hn> |
Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Sn> |
Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
| <Dn> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
AArch64_CheckFPEnabled(); let operand : bits(srcsize) = V{}(n); var result : bits(128) = if IsMerging(FPCR()) then V{128}(d) else Zeros{128}; result[0+:dstsize] = FPConvert{dstsize, srcsize}(operand, FPCR()); V{128}(d) = result;
2026-03_rel 2026-03-26 20:48:11
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