FCVTNT (unpredicated)

Single-precision convert to interleaved 8-bit floating-point (top)

This instruction converts each single-precision element of the pair of source vectors to 8-bit floating-point while scaling the value by 2SInt(FPMR.NSCALE), and places the two-way interleaved results in the corresponding odd-numbered 8-bit elements of the destination vector, leaving the even-numbered elements unchanged. The 8-bit floating-point encoding format is selected by FPMR.F8D.

This instruction is unpredicated.

SVE2
((FEAT_SVE2 || FEAT_SME2) && FEAT_FP8)

313029282726252423222120191817161514131211109876543210
0110010100001010001111Zn0Zd
T

Encoding

FCVTNT <Zd>.B, { <Zn1>.S-<Zn2>.S }

Decode for this encoding

if ((!IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME2)) || !IsFeatureImplemented(FEAT_FP8)) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn::'0'); let d : integer = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Zn1>

Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.

<Zn2>

Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

Operation

CheckFPMREnabled(); if IsFeatureImplemented(FEAT_SME2) then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); end; let VL : integer{} = CurrentVL(); let elements : integer = VL DIV 32; var result : bits(VL) = Z{}(d); let operand1 : bits(VL) = Z{}(n+0); let operand2 : bits(VL) = Z{}(n+1); for e = 0 to elements-1 do let element1 : bits(32) = operand1[e*:32]; let element2 : bits(32) = operand2[e*:32]; result[(4*e + 1)*:8] = FPConvertFP8{8, 32}(element1, FPCR(), FPMR()); result[(4*e + 3)*:8] = FPConvertFP8{8, 32}(element2, FPCR(), FPMR()); end; Z{VL}(d) = result;


2026-03_rel 2026-03-26 20:48:11

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