FCVTPU (scalar)

Floating-point convert to unsigned integer, rounding toward plus infinity (scalar)

This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round towards Plus Infinity rounding mode, and writes the result to the general-purpose destination register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
sf0011110ftype101001000000RnRd
Srmodeopcode

Encoding for the Half-precision to 32-bit variant
(FEAT_FP16)

Applies when (sf == 0 && ftype == 11)

FCVTPU <Wd>, <Hn>

Encoding for the Half-precision to 64-bit variant
(FEAT_FP16)

Applies when (sf == 1 && ftype == 11)

FCVTPU <Xd>, <Hn>

Encoding for the Single-precision to 32-bit variant
(FEAT_FP)

Applies when (sf == 0 && ftype == 00)

FCVTPU <Wd>, <Sn>

Encoding for the Single-precision to 64-bit variant
(FEAT_FP)

Applies when (sf == 1 && ftype == 00)

FCVTPU <Xd>, <Sn>

Encoding for the Double-precision to 32-bit variant
(FEAT_FP)

Applies when (sf == 0 && ftype == 01)

FCVTPU <Wd>, <Dn>

Encoding for the Double-precision to 64-bit variant
(FEAT_FP)

Applies when (sf == 1 && ftype == 01)

FCVTPU <Xd>, <Dn>

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if ftype == '10' then EndOfDecode(Decode_UNDEF); end; if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let intsize : integer{} = 32 << UInt(sf); let fltsize : integer{} = 8 << UInt(ftype XOR '10'); let rounding : FPRounding = FPRounding_POSINF; let unsigned : boolean = TRUE;

Assembler Symbols

<Wd>

Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Hn>

Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<Xd>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Sn>

Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<Dn>

Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

AArch64_CheckFPEnabled(); let fltval : bits(fltsize) = V{}(n); let fracbits : integer = 0; X{intsize}(d) = FPToFixed{intsize, fltsize}(fltval, fracbits, unsigned, FPCR(), rounding);

Operational information

If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the general-purpose register written by this instruction might be significantly delayed.


2026-03_rel 2026-03-26 20:48:11

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