Multi-vector single-precision convert to unsigned 32-bit integer, rounding toward zero
This instruction converts each element of the two or four source vectors from single-precision to the unsigned 32-bit integer nearer to zero, and places the results in the corresponding elements of the two or four destination vectors.
This instruction follows SME2 floating-point numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors.
This instruction is unpredicated.
It has encodings from 2 classes: Two registers and Four registers
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 1 | Zd | 0 | ||||||
| U | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn::'0'); let d : integer = UInt(Zd::'0'); let nreg : integer{} = 2; let unsigned : boolean = TRUE; let rounding : FPRounding = FPRounding_ZERO;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 0 | 1 | Zd | 0 | 0 | ||||
| U | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn::'00'); let d : integer = UInt(Zd::'00'); let nreg : integer{} = 4; let unsigned : boolean = TRUE; let rounding : FPRounding = FPRounding_ZERO;
| <Zd2> |
Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1. |
| <Zn2> |
Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1. |
| <Zd4> |
Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3. |
| <Zn4> |
Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3. |
CheckStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV 32; var results : array [[4]] of bits(VL); for r = 0 to nreg-1 do let operand : bits(VL) = Z{}(n+r); for e = 0 to elements-1 do let element : bits(32) = operand[e*:32]; results[[r]][e*:32] = FPToFixed{32, 32}(element, 0, unsigned, FPCR(), rounding); end; end; for r = 0 to nreg-1 do Z{VL}(d+r) = results[[r]]; end;
2026-03_rel 2026-03-26 20:48:11
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