FDOT (8-bit floating-point to half-precision, by element)

8-bit floating-point dot product to half-precision (vector, by element)

This instruction calculates the fused sum-of-products of a pair of 8-bit floating-point values held in each 16-bit element of the first source vector and a pair of 8-bit floating-point values in an indexed 16-bit element of the second source vector. The half-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE[3:0]), before being destructively added without intermediate rounding to the corresponding half-precision elements of the destination vector.

The 8-bit floating-point groups within the second source vector are specified using an immediate index.

The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.

Advanced SIMD
(FEAT_FP8DOT2)

313029282726252423222120191817161514131211109876543210
0Q00111101LMRm0000H0RnRd
Usizeopcode

Encoding

FDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.2B[<index>]

Decode for this encoding

if !IsFeatureImplemented(FEAT_FP8DOT2) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Rn); let d : integer = UInt(Rd); let m : integer = UInt('0'::Rm); let i : integer = UInt(H::L::M); let datasize : integer{} = if Q == '1' then 128 else 64; let esize : integer{} = 16; let elements : integer = datasize DIV esize;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta>

Is an arrangement specifier, encoded in Q:

Q <Ta>
0 4H
1 8H
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Tb>

Is an arrangement specifier, encoded in Q:

Q <Tb>
0 8B
1 16B
<Vm>

Is the name of the second SIMD&FP source register, in the range V0 to V15, encoded in the "Rm" field.

<index>

Is the immediate index of a pair of 8-bit elements, in the range 0 to 7, encoded in the "H:L:M" fields.

Operation

CheckFPMREnabled(); AArch64_CheckFPAdvSIMDEnabled(); let operand1 : bits(datasize) = V{}(n); let operand2 : bits(128) = V{}(m); let operand3 : bits(datasize) = V{}(d); var result : bits(datasize); for e = 0 to elements-1 do let op1 : bits(esize) = operand1[e*:esize]; let op2 : bits(esize) = operand2[i*:esize]; let sum : bits(esize) = operand3[e*:esize]; result[e*:esize] = FP8DotAddFP{esize, esize}(sum, op1, op2, FPCR(), FPMR()); end; V{datasize}(d) = result;


2026-03_rel 2026-03-26 20:48:11

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