FDOT (2-way, indexed, FP8 to FP16)

8-bit floating-point dot product by indexed element to half-precision

This instruction calculates the fused sum-of-products of a pair of 8-bit floating-point values held in each 16-bit element of the first source vector and a pair of 8-bit floating-point values in an indexed 16-bit element of the second source vector. The half-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE[3:0]), before being destructively added without intermediate rounding to the corresponding half-precision elements of the destination vector.

The 8-bit floating-point groups within the second source vector are specified using an immediate index that selects the same group position within each 128-bit vector segment. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively.

This instruction is unpredicated.

SVE2
((FEAT_SVE2 && FEAT_FP8DOT2) || FEAT_SSVE_FP8DOT2)

313029282726252423222120191817161514131211109876543210
01100100001i3hZm0100i3l1ZnZda
op

Encoding

FDOT <Zda>.H, <Zn>.B, <Zm>.B[<imm>]

Decode for this encoding

if !HaveSVE2FP8DOT2() then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda); let index : integer = UInt(i3h::i3l);

Assembler Symbols

<Zda>

Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.

<imm>

Is the immediate index of a pair of 8-bit elements within each 128-bit vector segment, in the range 0 to 7, encoded in the "i3h:i3l" fields.

Operation

CheckFPMREnabled(); if IsFeatureImplemented(FEAT_SSVE_FP8DOT2) && IsFeatureImplemented(FEAT_FP8DOT2) then CheckSVEEnabled(); elsif IsFeatureImplemented(FEAT_FP8DOT2) then CheckNonStreamingSVEEnabled(); else CheckStreamingSVEEnabled(); end; let VL : integer{} = CurrentVL(); let elements : integer = VL DIV 16; let eltspersegment : integer = 128 DIV 16; let operand1 : bits(VL) = Z{}(n); let operand2 : bits(VL) = Z{}(m); let operand3 : bits(VL) = Z{}(da); var result : bits(VL); for e = 0 to elements-1 do let segmentbase : integer = e - (e MOD eltspersegment); let s : integer = segmentbase + index; let op1 : bits(16) = operand1[e*:(16)]; let op2 : bits(16) = operand2[s*:(16)]; var sum : bits(16) = operand3[e*:(16)]; sum = FP8DotAddFP{16, 16}(sum, op1, op2, FPCR(), FPMR()); result[e*:(16)] = sum; end; Z{VL}(da) = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:


2026-03_rel 2026-03-26 20:48:11

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