FEXPA

Floating-point exponential accelerator

This instruction calculates an exponentiation acceleration operation on each floating-point element in the source vector, where the result sign is zero, the result exponent field is copied from a set of significant bits of the input fraction, and the result fraction is inserted from a lookup table indexed by the least-significant input fraction bits, and returns each result in the corresponding element of the destination vector.

This instruction is fully defined by its bit-manipulation semantics, does not generate floating-point exceptions, and does not guarantee NaN propagation.

For double-precision variants, the result element exponent is copied from the source element bits<16:6>, and the result fraction is set based on the source element to the rounded value of 252 × (2bits<5:0>/64 - 1).

For single-precision variants, the result element exponent is copied from the source element bits<13:6>, and the result fraction is set based on the source element to the rounded value of 223 × (2bits<5:0>/64 - 1).

For half-precision variants, the result element exponent is copied from the source element bits<9:5>, and the result fraction is set based on the source element to the rounded value of 210 × (2bits<4:0>/32 - 1).

This instruction is unpredicated.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled, or FEAT_SSVE_FEXPA is implemented.


Note

For a double-precision input value x in the range 70,368,744,177,655 <= x < 70,368,744,179,711, the operation performed by this instruction is equivalent to calculating 2x-70,368,744,178,687.

For a single-precision input value x in the range 131,073 <= x < 131,327, the operation performed by this instruction is equivalent to calculating 2x-131,199.

For a half-precision input value x in the range 33 <= x < 63, the operation performed by this instruction is equivalent to calculating 2x-47.


SVE
(FEAT_SVE || FEAT_SSVE_FEXPA)

313029282726252423222120191817161514131211109876543210
00000100size100000101110ZnZd
opc

Encoding

FEXPA <Zd>.<T>, <Zn>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SSVE_FEXPA) then EndOfDecode(Decode_UNDEF); end; if size == '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Zn); let d : integer = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 RESERVED
01 H
10 S
11 D
<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

Operation

if IsFeatureImplemented(FEAT_SSVE_FEXPA) then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); end; let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let operand : bits(VL) = Z{}(n); var result : bits(VL); for e = 0 to elements-1 do let element : bits(esize) = operand[e*:esize]; result[e*:esize] = FPExpA{esize}(element); end; Z{VL}(d) = result;


2026-03_rel 2026-03-26 20:48:11

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