Floating-point fused multiply-add (scalar)
This instruction multiplies the values of the first two SIMD&FP source registers, adds the product to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | ftype | 0 | Rm | 0 | Ra | Rn | Rd | |||||||||||||||||
| M | S | o1 | o0 | ||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if ftype == '10' then EndOfDecode(Decode_UNDEF); end; if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let a : integer{} = UInt(Ra); let esize : integer{} = 8 << UInt(ftype XOR '10');
| <Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Hn> |
Is the 16-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field. |
| <Hm> |
Is the 16-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field. |
| <Ha> |
Is the 16-bit name of the third SIMD&FP source register holding the addend, encoded in the "Ra" field. |
| <Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Sn> |
Is the 32-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field. |
| <Sm> |
Is the 32-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field. |
| <Sa> |
Is the 32-bit name of the third SIMD&FP source register holding the addend, encoded in the "Ra" field. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Dn> |
Is the 64-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field. |
| <Dm> |
Is the 64-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field. |
| <Da> |
Is the 64-bit name of the third SIMD&FP source register holding the addend, encoded in the "Ra" field. |
AArch64_CheckFPEnabled(); let addend : bits(esize) = V{esize}(a); let operand1 : bits(esize) = V{esize}(n); let operand2 : bits(esize) = V{}(m); var result : bits(128) = if IsMerging(FPCR()) then V{128}(a) else Zeros{128}; result[0+:esize] = FPMulAdd{esize}(addend, operand1, operand2, FPCR()); V{128}(d) = result;
2026-03_rel 2026-03-26 20:48:11
Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.