FMAXNMP (scalar)

Floating-point maximum number of pair of elements (scalar)

This instruction compares two vector elements in the source SIMD&FP register and writes the largest of the floating-point values as a scalar to the destination SIMD&FP register.

Regardless of the value of FPCR.AH, the behavior is as follows for each pairwise operation:

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Half-precision and Single-precision and double-precision

Half-precision
(FEAT_AdvSIMD && FEAT_FP16)

313029282726252423222120191817161514131211109876543210
0101111000110000110010RnRd
Uo1szopcode

Encoding

FMAXNMP H<d>, <Vn>.2H

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; if sz == '1' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 16; let datasize : integer{} = 32;

Single-precision and double-precision
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
011111100sz110000110010RnRd
Uo1opcode

Encoding

FMAXNMP <V><d>, <Vn>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 32 << UInt(sz); let datasize : integer{} = esize * 2;

Assembler Symbols

<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<V>

Is the destination width specifier, encoded in sz:

sz <V>
0 S
1 D
<T>

Is the source arrangement specifier, encoded in sz:

sz <T>
0 2S
1 2D

Operation

AArch64_CheckFPAdvSIMDEnabled(); let operand : bits(datasize) = V{}(n); let element1 : bits(esize) = operand[0*:esize]; let element2 : bits(esize) = operand[1*:esize]; V{esize}(d) = FPMaxNum{esize}(element1, element2, FPCR());


2026-03_rel 2026-03-26 20:48:11

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