FMAXV

Floating-point maximum recursive reduction to scalar

This instruction calculates a floating-point maximum horizontally over all lanes of a vector using a recursive pairwise reduction, and places the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as -Infinity.

When FPCR.AH is 0, the behavior is as follows:

When FPCR.AH is 1, the behavior is as follows:

SVE
(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
01100101size000110001PgZnVd
opc

Encoding

FMAXV <V><d>, <Pg>, <Zn>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; if size == '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let d : integer = UInt(Vd);

Assembler Symbols

<V>

Is a width specifier, encoded in size:

size <V>
00 RESERVED
01 H
10 S
11 D
<d>

Is the number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 RESERVED
01 H
10 S
11 D

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let mask : bits(PL) = P{}(g); let operand : bits(VL) = if AnyActiveElement{PL}(mask, esize) then Z{VL}(n) else Zeros{VL}; let identity : bits(esize) = FPInfinity{esize}('1'); V{esize}(d) = FPReducePredicated{esize, VL, PL}(ReduceOp_FMAX, operand, mask, identity, FPCR());


2026-03_rel 2026-03-26 20:48:11

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