FMLALB, FMLALT (vector)

8-bit floating-point multiply-add to half-precision (vector)

This instruction widens the even-numbered (bottom) or odd-numbered (top) 8-bit elements in the first and second source vectors to half-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE[3:0]), before being destructively added without intermediate rounding to the half-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the source vectors.

The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.

Advanced SIMD
(FEAT_FP8FMA)

313029282726252423222120191817161514131211109876543210
0Q001110110Rm111111RnRd
Usizeopcode

Encoding for the FMLALB variant

Applies when (Q == 0)

FMLALB <Vd>.8H, <Vn>.16B, <Vm>.16B

Encoding for the FMLALT variant

Applies when (Q == 1)

FMLALT <Vd>.8H, <Vn>.16B, <Vm>.16B

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FP8FMA) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let elements : integer = 128 DIV 16; let sel : integer = UInt(Q);

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPMREnabled(); AArch64_CheckFPAdvSIMDEnabled(); let operand1 : bits(128) = V{}(n); let operand2 : bits(128) = V{}(m); let operand3 : bits(128) = V{}(d); var result : bits(128); for e = 0 to elements-1 do let element1 : bits(8) = operand1[(2 * e + sel)*:8]; let element2 : bits(8) = operand2[(2 * e + sel)*:8]; let element3 : bits(16) = operand3[e*:16]; result[e*:16] = FP8MulAddFP{16}(element3, element1, element2, FPCR(), FPMR()); end; V{128}(d) = result;


2026-03_rel 2026-03-26 20:48:11

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