8-bit floating-point multiply-add by indexed element to single-precision (bottom bottom)
This instruction widens the first 8-bit element of each 32-bit container in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE) before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the first source vector. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively.
This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | i4h | Zm | 1 | 1 | 0 | 0 | i4l | Zn | Zda | ||||||||||||
| TT | |||||||||||||||||||||||||||||||
if !HaveSVE2FP8FMA() then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda); let index : integer = UInt(i4h::i4l);
| <Zda> |
Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. |
| <imm> |
Is the immediate index, in the range 0 to 15, encoded in the "i4h:i4l" fields. |
CheckFPMREnabled(); if IsFeatureImplemented(FEAT_SSVE_FP8FMA) && IsFeatureImplemented(FEAT_FP8FMA) then CheckSVEEnabled(); elsif IsFeatureImplemented(FEAT_FP8FMA) then CheckNonStreamingSVEEnabled(); else CheckStreamingSVEEnabled(); end; let VL : integer{} = CurrentVL(); let elements : integer = VL DIV 32; let eltspersegment : integer = 128 DIV 32; let operand1 : bits(VL) = Z{}(n); let operand2 : bits(VL) = Z{}(m); let operand3 : bits(VL) = Z{}(da); var result : bits(VL); for e = 0 to elements-1 do let segmentbase : integer = e - (e MOD eltspersegment); let s : integer = 4 * segmentbase + index; let element1 : bits(8) = operand1[(4 * e + 0)*:8]; let element2 : bits(8) = operand2[s*:8]; let element3 : bits(32) = operand3[e*:32]; result[e*:32] = FP8MulAddFP{32}(element3, element1, element2, FPCR(), FPMR()); end; Z{VL}(da) = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:
2026-03_rel 2026-03-26 20:48:11
Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.