Multi-vector floating-point fused multiply-subtract by indexed element
This instruction multiplies the indexed element of the second source vector by the corresponding floating-point elements of the two or four first source vectors and destructively subtracts these values without intermediate rounding from the corresponding elements of the ZA single-vector groups.
The elements within the second source vector are specified using an immediate element index that selects the same element position within each 128-bit vector segment. The index range is from 0 to one less than the number of elements per 128-bit segment.
The single-vector group within each half of or each quarter of the ZA array is selected by the sum of the vector select register and offset, modulo half or quarter the number of ZA array vectors.
The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.
This instruction follows SME ZA-targeting floating-point behaviors.
This instruction is unpredicated.
ID_AA64SMFR0_EL1.F64F64 indicates whether the double-precision variant is implemented, and ID_AA64SMFR0_EL1.F16F16 indicates whether the half-precision variant is implemented.
It has encodings from 6 classes: Two ZA single-vectors of half-precision elements , Two ZA single-vectors of single-precision elements , Two ZA single-vectors of double-precision elements , Four ZA single-vectors of half-precision elements , Four ZA single-vectors of single-precision elements and Four ZA single-vectors of double-precision elements
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | Zm | 0 | Rv | 1 | i3h | Zn | 0 | 1 | i3l | off3 | ||||||||||
| op | S | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME_F16F16) then EndOfDecode(Decode_UNDEF); end; let v : integer = UInt('010'::Rv); let esize : integer{} = 16; let n : integer = UInt(Zn::'0'); let m : integer = UInt('0'::Zm); let offset : integer = UInt(off3); let index : integer = UInt(i3h::i3l); let nreg : integer{} = 2;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | Zm | 0 | Rv | 0 | i2 | Zn | 0 | 1 | 0 | off3 | ||||||||||
| op | S | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let v : integer = UInt('010'::Rv); let esize : integer{} = 32; let n : integer = UInt(Zn::'0'); let m : integer = UInt('0'::Zm); let offset : integer = UInt(off3); let index : integer = UInt(i2); let nreg : integer{} = 2;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | Zm | 0 | Rv | 0 | 0 | i1 | Zn | 0 | 1 | 0 | off3 | |||||||||
| S | |||||||||||||||||||||||||||||||
if !(IsFeatureImplemented(FEAT_SME2) && IsFeatureImplemented(FEAT_SME_F64F64)) then EndOfDecode(Decode_UNDEF); end; let v : integer = UInt('010'::Rv); let esize : integer{} = 64; let n : integer = UInt(Zn::'0'); let m : integer = UInt('0'::Zm); let offset : integer = UInt(off3); let index : integer = UInt(i1); let nreg : integer{} = 2;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | Zm | 1 | Rv | 1 | i3h | Zn | 0 | 0 | 1 | i3l | off3 | |||||||||
| op | S | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME_F16F16) then EndOfDecode(Decode_UNDEF); end; let v : integer = UInt('010'::Rv); let esize : integer{} = 16; let n : integer = UInt(Zn::'00'); let m : integer = UInt('0'::Zm); let offset : integer = UInt(off3); let index : integer = UInt(i3h::i3l); let nreg : integer{} = 4;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | Zm | 1 | Rv | 0 | i2 | Zn | 0 | 0 | 1 | 0 | off3 | |||||||||
| op | S | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let v : integer = UInt('010'::Rv); let esize : integer{} = 32; let n : integer = UInt(Zn::'00'); let m : integer = UInt('0'::Zm); let offset : integer = UInt(off3); let index : integer = UInt(i2); let nreg : integer{} = 4;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | Zm | 1 | Rv | 0 | 0 | i1 | Zn | 0 | 0 | 1 | 0 | off3 | ||||||||
| op | S | ||||||||||||||||||||||||||||||
if !(IsFeatureImplemented(FEAT_SME2) && IsFeatureImplemented(FEAT_SME_F64F64)) then EndOfDecode(Decode_UNDEF); end; let v : integer = UInt('010'::Rv); let esize : integer{} = 64; let n : integer = UInt(Zn::'00'); let m : integer = UInt('0'::Zm); let offset : integer = UInt(off3); let index : integer = UInt(i1); let nreg : integer{} = 4;
| <Wv> |
Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field. |
| <offs> |
Is the vector select offset, in the range 0 to 7, encoded in the "off3" field. |
| <Zn2> |
Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" times 2 plus 1. |
| <Zm> |
Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. |
| <Zn4> |
Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" times 4 plus 3. |
CheckStreamingSVEAndZAEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let vectors : integer = VL DIV 8; let vstride : integer = vectors DIV nreg; let eltspersegment : integer = 128 DIV esize; let vbase : bits(32) = X{}(v); var vec : integer = (UInt(vbase) + offset) MOD vstride; var result : bits(VL); for r = 0 to nreg-1 do let op1 : bits(VL) = Z{}(n+r); let op2 : bits(VL) = Z{}(m); let op3 : bits(VL) = ZAvector{}(vec); for e = 0 to elements-1 do let elem1 : bits(esize) = FPNeg{}(op1[e*:esize], FPCR()); let segmentbase : integer = e - (e MOD eltspersegment); let s : integer = segmentbase + index; let elem2 : bits(esize) = op2[s*:esize]; let elem3 : bits(esize) = op3[e*:esize]; result[e*:esize] = FPMulAdd_ZA{esize}(elem3, elem1, elem2, FPCR()); end; ZAvector{VL}(vec) = result; vec = vec + vstride; end;
2026-03_rel 2026-03-26 20:48:11
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