FMLSLT (indexed)

Half-precision multiply-subtract by indexed element from single-precision (top)

This instruction widens the odd-numbered half-precision elements in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to single-precision format and then destructively multiplies and subtracts these values without intermediate rounding from the single-precision elements of the destination vector that overlap with the corresponding half-precision elements in the first source vector. This instruction is unpredicated.

Single-precision
(FEAT_SVE2 || FEAT_SME)

313029282726252423222120191817161514131211109876543210
01100100101i3hZm0110i3l1ZnZda
o2opT

Encoding

FMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda); let index : integer = UInt(i3h::i3l); let op1_neg : boolean = TRUE;

Assembler Symbols

<Zda>

Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.

<imm>

Is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let eltspersegment : integer = 128 DIV esize; let op1 : bits(VL) = Z{}(n); let op2 : bits(VL) = Z{}(m); let op3 : bits(VL) = Z{}(da); var result : bits(VL); for e = 0 to elements-1 do let segmentbase : integer = e - (e MOD eltspersegment); let s : integer = 2 * segmentbase + index; let elem1 : bits(esize DIV 2) = (if op1_neg then FPNeg{esize DIV 2}(op1[(2*e + 1)*:(esize DIV 2)], FPCR()) else op1[(2*e + 1)*:(esize DIV 2)]); let elem2 : bits(esize DIV 2) = op2[s*:(esize DIV 2)]; let elem3 : bits(esize) = op3[e*:esize]; result[e*:esize] = FPMulAddH(elem3, elem1, elem2, FPCR()); end; Z{VL}(da) = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:


2026-03_rel 2026-03-26 20:48:11

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