FMMLA (widening, 8-bit floating-point to single-precision) -- A64

This instruction multiplies the 2×8 matrix of 8-bit floating-point values held in the first source vector by the 8×2 matrix of 8-bit floating-point values in the second source vector. The intermediate single-precision results, calculated as a fused sum-of-products using eight adjacent 8-bit floating-point values from each of the source vectors, are scaled by 2^{-UInt(FPMR.LSCALE)} before being destructively added without intermediate rounding to the 2x2 single-precision matrix in the destination vector. This is equivalent to accumulating 8-way dot product per destination element.

The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.

Advanced SIMD
(FEAT_F8F32MM)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	1	1	1	0	1	0	0	Rm					1	1	1	0	1	1	Rn					Rd
	Q	U						size									opcode

Decode for this encoding

if !IsFeatureImplemented(FEAT_F8F32MM) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Rn); let m : integer = UInt(Rm); let d : integer = UInt(Rd);

Assembler Symbols

<Vd>	Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field.

<Vn>	Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>	Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPMREnabled(); AArch64_CheckFPAdvSIMDEnabled(); let op1 : bits(128) = V{}(n); let op2 : bits(128) = V{}(m); let acc : bits(128) = V{}(d); V{128}(d) = FP8MatMulAddFP{128}(acc, op1, op2, 8, FPCR(), FPMR());

2026-03_rel 2026-03-26 20:48:11