FMMLA (widening, FP16 to FP32)

Half-precision matrix multiply-accumulate to single-precision

This instruction multiplies the 2×4 matrix of half-precision values held in each 128-bit segment of the first source vector by the 4×2 matrix of half-precision values in the corresponding segment of the second source vector. The intermediate single-precision results are calculated as a sum of two fused sum-of-products using two pairs of adjacent half-precision values from each of the source vectors, and rounded before accumulation into the 2×2 matrix of single-precision results in the corresponding segment of the destination vector. This is equivalent to performing a 4-way dot product per destination element.

This instruction is unpredicated.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

SVE2
(FEAT_SVE_F16F32MM)

313029282726252423222120191817161514131211109876543210
01100100001Zm111001ZnZda
opc

Encoding

FMMLA <Zda>.S, <Zn>.H, <Zm>.H

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE_F16F32MM) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda);

Assembler Symbols

<Zda>

Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let segments : integer = VL DIV 128; let operand1 : bits(VL) = Z{}(n); let operand2 : bits(VL) = Z{}(m); let operand3 : bits(VL) = Z{}(da); var result : bits(VL); for s = 0 to segments-1 do let op1 : bits(128) = operand1[s*:(128)]; let op2 : bits(128) = operand2[s*:(128)]; let addend : bits(128) = operand3[s*:(128)]; result[s*:(128)] = FPMatMulAddH{128}(addend, op1, op2, FPCR()); end; Z{VL}(da) = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:


2026-03_rel 2026-03-26 20:48:11

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