FMOPA (widening, 4-way)

8-bit floating-point sum of outer products to single-precision, accumulating

This instruction works with a 32-bit element ZA tile.

This instruction widens the SVLS×4 sub-matrix of 8-bit floating-point values held in the first source vector to single-precision values and multiplies it by the widened 4×SVLS sub-matrix of 8-bit floating-point values in the second source vector to single-precision values.

Each source vector is independently predicated by a corresponding governing predicate. When a 8-bit source element is Inactive it is treated as having the value +0.0, but if both groups of source vector elements that correspond to a 32-bit destination element contain Inactive elements, then the destination element remains unmodified.

The resulting SVLS×SVLS single-precision sum of outer products are scaled by 2-UInt(FPMR.LSCALE), before being destructively added to the single-precision destination tile. This is equivalent to performing a downscaled 4-way dot product and accumulate to each of the destination tile elements.

Each 32-bit container of the first source vector holds 4 consecutive column elements of each row of a SVLS×4 sub-matrix. Similarly, each 32-bit container of the second source vector holds 4 consecutive row elements of each column of a 4×SVLS sub-matrix.

The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively.

SME2
(FEAT_SME_F8F32)

313029282726252423222120191817161514131211109876543210
10000000101ZmPmPnZn000ZAda

Encoding

FMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_F8F32) then EndOfDecode(Decode_UNDEF); end; let a : integer = UInt(Pn); let b : integer = UInt(Pm); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(ZAda);

Assembler Symbols

<ZAda>

Is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field.

<Pn>

Is the name of the first governing scalable predicate register P0-P7, encoded in the "Pn" field.

<Pm>

Is the name of the second governing scalable predicate register P0-P7, encoded in the "Pm" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckFPMREnabled(); CheckStreamingSVEAndZAEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let dim : integer{} = VL DIV 32; let mask1 : bits(PL) = P{}(a); let mask2 : bits(PL) = P{}(b); let operand1 : bits(VL) = Z{}(n); let operand2 : bits(VL) = Z{}(m); let operand3 : bits(dim*dim*32) = ZAtile{}(da, 32); var result : bits(dim*dim*32); for row = 0 to dim-1 do for col = 0 to dim-1 do var prow : array [[4]] of boolean; var pcol : array [[4]] of boolean; var any_active : boolean = FALSE; for i = 0 to 3 do prow[[i]] = ActivePredicateElement{PL}(mask1, 4*row + i, 8); pcol[[i]] = ActivePredicateElement{PL}(mask2, 4*col + i, 8); any_active = any_active || (prow[[i]] && pcol[[i]]); end; if any_active then var sum : bits(32) = operand3[(row*dim+col)*:32]; var rowop : bits(32) = Zeros{}; var colop : bits(32) = Zeros{}; for i = 0 to 3 do if prow[[i]] then rowop[i*:8] = operand1[(4*row + i)*:8]; end; if pcol[[i]] then colop[i*:8] = operand2[(4*col + i)*:8]; end; end; sum = FP8DotAddFP{32, 32}(sum, rowop, colop, FPCR(), FPMR()); result[(row*dim+col)*:32] = sum; else result[(row*dim+col)*:32] = operand3[(row*dim+col)*:32]; end; end; end; ZAtile{dim*dim*32}(da, 32) = result;


2026-03_rel 2026-03-26 20:48:11

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