FMOV (general)

Floating-point move to or from general-purpose register without conversion

This instruction transfers the contents of a SIMD&FP register to a general-purpose register, or the contents of a general-purpose register to a SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
sf0011110ftype10x11x000000RnRd
Srmodeopcode

Encoding for the Half-precision to 32-bit variant
(FEAT_FP16)

Applies when (sf == 0 && ftype == 11 && rmode == 00 && opcode == 110)

FMOV <Wd>, <Hn>

Encoding for the Half-precision to 64-bit variant
(FEAT_FP16)

Applies when (sf == 1 && ftype == 11 && rmode == 00 && opcode == 110)

FMOV <Xd>, <Hn>

Encoding for the 32-bit to half-precision variant
(FEAT_FP16)

Applies when (sf == 0 && ftype == 11 && rmode == 00 && opcode == 111)

FMOV <Hd>, <Wn>

Encoding for the 32-bit to single-precision variant
(FEAT_FP)

Applies when (sf == 0 && ftype == 00 && rmode == 00 && opcode == 111)

FMOV <Sd>, <Wn>

Encoding for the Single-precision to 32-bit variant
(FEAT_FP)

Applies when (sf == 0 && ftype == 00 && rmode == 00 && opcode == 110)

FMOV <Wd>, <Sn>

Encoding for the 64-bit to half-precision variant
(FEAT_FP16)

Applies when (sf == 1 && ftype == 11 && rmode == 00 && opcode == 111)

FMOV <Hd>, <Xn>

Encoding for the 64-bit to double-precision variant
(FEAT_FP)

Applies when (sf == 1 && ftype == 01 && rmode == 00 && opcode == 111)

FMOV <Dd>, <Xn>

Encoding for the 64-bit to top half of 128-bit variant
(FEAT_FP)

Applies when (sf == 1 && ftype == 10 && rmode == 01 && opcode == 111)

FMOV <Vd>.D[1], <Xn>

Encoding for the Double-precision to 64-bit variant
(FEAT_FP)

Applies when (sf == 1 && ftype == 01 && rmode == 00 && opcode == 110)

FMOV <Xd>, <Dn>

Encoding for the Top half of 128-bit to 64-bit variant
(FEAT_FP)

Applies when (sf == 1 && ftype == 10 && rmode == 01 && opcode == 110)

FMOV <Xd>, <Vn>.D[1]

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if ftype == '10' && opcode[2:1]::rmode != '11 01' then EndOfDecode(Decode_UNDEF); end; if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let intsize : integer{} = 32 << UInt(sf); let fltsize : integer{} = if ftype == '10' then 64 else (8 << UInt(ftype XOR '10')); let part : integer = UInt(rmode[0]); var op : FPConvOp; case opcode[2:1]::rmode of when '11 00' => // FMOV if fltsize != 16 && fltsize != intsize then EndOfDecode(Decode_UNDEF); end; op = if opcode[0] == '1' then FPConvOp_MOV_ItoF else FPConvOp_MOV_FtoI; when '11 01' => // FMOV D[1] if intsize != 64 || ftype != '10' then EndOfDecode(Decode_UNDEF); end; op = if opcode[0] == '1' then FPConvOp_MOV_ItoF else FPConvOp_MOV_FtoI; otherwise => unreachable; end;

Assembler Symbols

<Wd>

Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Hn>

Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<Xd>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Hd>

Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Wn>

Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Sn>

Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<Xn>

Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Dn>

Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

AArch64_CheckFPEnabled(); var fltval : bits(fltsize); var intval : bits(intsize); case op of when FPConvOp_MOV_FtoI => fltval = Vpart{fltsize}(n, part); X{intsize}(d) = ZeroExtend{intsize}(fltval); when FPConvOp_MOV_ItoF => intval = X{intsize}(n); Vpart{fltsize}(d, part) = intval[fltsize-1:0]; otherwise => unreachable; end;

Operational information

If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the general-purpose register written by this instruction might be significantly delayed.


2026-03_rel 2026-03-26 20:48:11

Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.