FMOV (scalar, immediate)

Floating-point move immediate (scalar)

This instruction copies a floating-point immediate constant into the SIMD&FP destination register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
00011110ftype1imm810000000Rd
MSimm5

Encoding for the Half-precision variant
(FEAT_FP16)

Applies when (ftype == 11)

FMOV <Hd>, #<imm>

Encoding for the Single-precision variant
(FEAT_FP)

Applies when (ftype == 00)

FMOV <Sd>, #<imm>

Encoding for the Double-precision variant
(FEAT_FP)

Applies when (ftype == 01)

FMOV <Dd>, #<imm>

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if ftype == '10' then EndOfDecode(Decode_UNDEF); end; if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let datasize : integer{} = 8 << UInt(ftype XOR '10'); let imm : bits(datasize) = VFPExpandImm{}(imm8);

Assembler Symbols

<Hd>

Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<imm>

Is a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, encoded in the "imm8" field. For details of the range of constants available and the encoding of <imm>, see Modified immediate constants in A64 floating-point instructions.

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

Operation

AArch64_CheckFPEnabled(); V{datasize}(d) = imm;


2026-03_rel 2026-03-26 20:48:11

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