FMUL (multiple and single vector) -- A64

This instruction multiplies all the floating-point elements of the two or four first source vectors by the corresponding floating-point elements of the second source vector, and places the results in the corresponding elements of the two or four destination vectors.

This instruction follows SME2 floating-point numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors.

Two registers
(FEAT_SME2p2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2p2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let d : integer = UInt(Zd::'0'); let n : integer = UInt(Zn::'0'); let m : integer = UInt('0'::Zm); let nreg : integer{} = 2;

Four registers
(FEAT_SME2p2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2p2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let d : integer = UInt(Zd::'00'); let n : integer = UInt(Zn::'00'); let m : integer = UInt('0'::Zm); let nreg : integer{} = 4;

Assembler Symbols

<Zd1>	For the "Two registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.
	For the "Four registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.

<T>

Is the size specifier, encoded in size:

size	<T>
01	H
10	S
11	D

<Zd2>

Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.

<Zn1>	For the "Two registers" variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 2.
	For the "Four registers" variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 4.

<Zn2>

Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" times 2 plus 1.

<Zm>	Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.

<Zd4>

Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.

<Zn4>

Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" times 4 plus 3.

Operation

CheckStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; var results : array [[4]] of bits(VL); for r = 0 to nreg-1 do let operand1 : bits(VL) = Z{}(n+r); let operand2 : bits(VL) = Z{}(m); for e = 0 to elements-1 do let element1 : bits(esize) = operand1[e*:(esize)]; let element2 : bits(esize) = operand2[e*:(esize)]; results[[r]][e*:(esize)] = FPMul{esize}(element1, element2, FPCR()); end; end; for r = 0 to nreg-1 do Z{VL}(d+r) = results[[r]]; end;

2026-03_rel 2026-03-26 20:48:11

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	0	0	1	!= 00		1	Zm				0	1	1	1	0	1	0	Zn				0	Zd				0
								size

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	0	0	1	!= 00		1	Zm				1	1	1	1	0	1	0	Zn			0	0	Zd			0	0
								size