Floating-point multiply extended (by element)
This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 4 classes: Scalar, half-precision , Scalar, single-precision and double-precision , Vector, half-precision and Vector, single-precision and double-precision
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | L | M | Rm | 1 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
| U | size | opcode | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; let idxdsize : integer{} = 64 << UInt(H); let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let index : integer = UInt(H::L::M); let esize : integer{} = 16; let datasize : integer{} = esize; let elements : integer = 1;
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| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | sz | L | M | Rm | 1 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
| U | opcode | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let idxdsize : integer{} = 64 << UInt(H); var index : integer; let Rmhi : bit = M; case sz::L of when '0x' => index = UInt(H::L); when '10' => index = UInt(H); when '11' => EndOfDecode(Decode_UNDEF); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rmhi::Rm); let esize : integer{} = 32 << UInt(sz); let datasize : integer{} = esize; let elements : integer = 1;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | L | M | Rm | 1 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
| U | size | opcode | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; let idxdsize : integer{} = 64 << UInt(H); let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let index : integer = UInt(H::L::M); let esize : integer{} = 16; let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV esize;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | 1 | sz | L | M | Rm | 1 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
| U | opcode | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let idxdsize : integer{} = 64 << UInt(H); var index : integer; let Rmhi : bit = M; case sz::L of when '0x' => index = UInt(H::L); when '10' => index = UInt(H); when '11' => EndOfDecode(Decode_UNDEF); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rmhi::Rm); if sz::Q == '10' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32 << UInt(sz); let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV esize;
| <Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Hn> |
Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field. |
| <V> |
Is a width specifier,
encoded in
|
| <d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
| <n> |
Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Ts> |
Is an element size specifier,
encoded in
|
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <T> |
For the "Vector, half-precision" variant: is an arrangement specifier,
encoded in
| |||||||||||||||
|
For the "Vector, single-precision and double-precision" variant: is an arrangement specifier,
encoded in
|
| <Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
AArch64_CheckFPAdvSIMDEnabled(); let operand1 : bits(datasize) = V{}(n); let operand2 : bits(idxdsize) = V{}(m); var element1 : bits(esize); let element2 : bits(esize) = operand2[index*:esize]; let merge : boolean = elements == 1 && IsMerging(FPCR()); var result : bits(128) = if merge then V{128}(n) else Zeros{128}; for e = 0 to elements-1 do element1 = operand1[e*:esize]; result[e*:esize] = FPMulX{esize}(element1, element2, FPCR()); end; V{128}(d) = result;
2026-03_rel 2026-03-26 20:48:11
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