FNMUL (scalar)

Floating-point multiply-negate (scalar)

This instruction multiplies the floating-point values of the two source SIMD&FP registers, and writes the negation of the result to the destination SIMD&FP register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
00011110ftype1Rm100010RnRd
MSop

Encoding for the Half-precision variant
(FEAT_FP16)

Applies when (ftype == 11)

FNMUL <Hd>, <Hn>, <Hm>

Encoding for the Single-precision variant
(FEAT_FP)

Applies when (ftype == 00)

FNMUL <Sd>, <Sn>, <Sm>

Encoding for the Double-precision variant
(FEAT_FP)

Applies when (ftype == 01)

FNMUL <Dd>, <Dn>, <Dm>

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if ftype == '10' then EndOfDecode(Decode_UNDEF); end; if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let esize : integer{} = 8 << UInt(ftype XOR '10');

Assembler Symbols

<Hd>

Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Hn>

Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.

<Hm>

Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Sn>

Is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.

<Sm>

Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Dn>

Is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.

<Dm>

Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

AArch64_CheckFPEnabled(); let operand1 : bits(esize) = V{}(n); let operand2 : bits(esize) = V{}(m); var result : bits(128) = if IsMerging(FPCR()) then V{128}(n) else Zeros{128}; let product : bits(esize) = FPMul{}(operand1, operand2, FPCR()); result[0+:esize] = FPNeg{esize}(product, FPCR()); V{128}(d) = result;


2026-03_rel 2026-03-26 20:48:11

Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.