Floating-point round to 64-bit integer (predicated)
This instruction rounds to integral floating-point values that fit into a 64-bit integer size using the rounding mode that is determined by the FPCR from each active floating-point element of the source vector, and places the results in the corresponding elements of the destination vector.
Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.
It has encodings from 2 classes: Merging and Zeroing
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | sz | 1 | 1 | 0 | 1 | Pg | Zn | Zd | ||||||||||
| opc | U | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32 << UInt(sz); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let intsize : integer{} = 64; let rounding : FPRounding = FPRoundingMode(FPCR()); let merging : boolean = TRUE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | sz | 1 | Pg | Zn | Zd | ||||||||||
| opc | o2 | U | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32 << UInt(sz); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let intsize : integer{} = 64; let rounding : FPRounding = FPRoundingMode(FPCR()); let merging : boolean = FALSE;
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); let operand : bits(VL) = if AnyActiveElement{PL}(mask, esize) then Z{VL}(n) else Zeros{VL}; var result : bits(VL) = if merging then Z{VL}(d) else Zeros{VL}; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then let element : bits(esize) = operand[e*:esize]; result[e*:esize] = FPRoundIntN{esize}(element, FPCR(), rounding, intsize); end; end; Z{VL}(d) = result;
For the "Merging" variant:
The merging variant of this instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and the merging variant of this instruction is CONSTRAINED UNPREDICTABLE:
2026-03_rel 2026-03-26 20:48:11
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