INSR (scalar)

Insert general-purpose register in shifted vector

This instruction shifts the destination vector left by one element, and then places a copy of the least-significant bits of the general-purpose register in element 0 of the destination vector. This instruction is unpredicated.

SVE
(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
00000101size100100001110RmZdn

Encoding

INSR <Zdn>.<T>, <R><m>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let dn : integer = UInt(Zdn); let m : integer = UInt(Rm);

Assembler Symbols

<Zdn>

Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D
<R>

Is a width specifier, encoded in size:

size <R>
00 W
01 W
10 W
11 X
<m>

Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let dest : bits(VL) = Z{}(dn); let src : bits(esize) = X{}(m); Z{VL}(dn) = dest[(VL-esize)-1:0] :: src;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:


2026-03_rel 2026-03-26 20:48:11

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