LASTB (scalar)

Extract last element to general-purpose register

This instruction extracts the Last active element to a general-purpose register. If there is an Active element, the Last active element from the final source vector register is extracted. If there are no Active elements, the highest-numbered element is extracted. Then the extracted element is zero-extended and placed in the destination general-purpose register.

SVE
(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
00000101size100001101PgZnRd
B

Encoding

LASTB <R><d>, <Pg>, <Zn>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let rsize : integer{} = if esize < 64 then 32 else 64; let g : integer = UInt(Pg); let n : integer = UInt(Zn); let d : integer = UInt(Rd); let isBefore : boolean = TRUE;

Assembler Symbols

<R>

Is a width specifier, encoded in size:

size <R>
00 W
01 W
10 W
11 X
<d>

Is the number [0-30] of the destination general-purpose register or the name ZR (31), encoded in the "Rd" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); let operand : bits(VL) = Z{}(n); var result : bits(rsize); var last : integer = LastActiveElement{PL}(mask, esize); if isBefore then if last < 0 then last = elements - 1; end; else last = last + 1; if last >= elements then last = 0; end; end; result = ZeroExtend{rsize}(operand[last*:esize]); X{rsize}(d) = result;

Operational information

If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the general-purpose register written by this instruction might be significantly delayed.


2026-03_rel 2026-03-26 20:48:11

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