LASTB (SIMD&FP scalar) -- A64

This instruction extracts the Last active element to a SIMD&FP scalar register. If there is an Active element, the Last active element from the final source vector register is extracted. If there are no Active elements, the highest-numbered element is extracted. Then the extracted element is placed in the destination SIMD&FP register.

SVE
(FEAT_SVE || FEAT_SME)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let d : integer = UInt(Vd); let isBefore : boolean = TRUE;

Assembler Symbols

<V>

Is a width specifier, encoded in size:

size	<V>
00	B
01	H
10	S
11	D

<d>	Is the number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>	Is the name of the source scalable vector register, encoded in the "Zn" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	D

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); let operand : bits(VL) = Z{}(n); var last : integer = LastActiveElement{PL}(mask, esize); if isBefore then if last < 0 then last = elements - 1; end; else last = last + 1; if last >= elements then last = 0; end; end; V{esize}(d) = operand[last*:esize];

2026-03_rel 2026-03-26 20:48:11

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	1	size		1	0	0	0	1	1	1	0	0	Pg			Zn					Vd
															B